The HDLC (high level data link control) protocol, established by international convention (ISO 3309), supports multiple sessions or addresses on a single link. In data transmission systems, such as a telephone switching system, HDLC frames are specified for a given address and must be processed based on the status of that address, independently of the status of other addresses.
The function of an HDLC engine is to emulate the behavior of multiple independent HDLC transmitters and receivers. In one hypothetical arrangement, there are twenty-five individual addresses and a broadcast address. The system keeps track of these individual addresses by way of a status table stored in the system's memory. The engine analyzes incoming HDLC frames and takes appropriate action, the actual response of the engine depends on the status of the address and the incoming frame type. In the systems under discussion, the engine would either discard the frame, generate the proper response, or pass the frame to the microprocessor or a dedicated HDLC controller.
To achieve the necessary performance, one could provide a separate HDLC engine for each address and each such engine would have an internal address status register. While this would eliminate the need for a dedicated memory holding the status of each address, the overall cost of the system would increase greatly due to the use of separate engines and the circuit board real estate required to accommodate these components.
Another method of handling the HDLC messages uses a single engine that passes the address of each frame to a microprocessor through a polling or interrupt process. The processor would use the address to access the status table in memory and notify the engine of the result so that the engine could take the appropriate action. Although it would simplify hardware requirements, this arrangement would tie up the microprocessor, preventing the microprocessor from tending to other tasks, and its ability to process incoming messages would be dependent on the microprocessor's speed.
A third solution would be to store an address status table in a dual-port RAM (random access memory) with processor access on one port and engine access on the other port. Although this scheme would eliminate the bottleneck caused by having to pass everything through the processor and would also improve the speed of the system, dual-port RAMs are expensive and would require additional board space.
The ideal solution therefore would minimize the use of the microprocessor and component count, without sacrificing efficiency.